Hana-1: Programmable I/O for FPGAs

Hana-1 îs a programable soft core I/O processor for FPGAs. Instead of designing a circuit, just program your desired I/O functionality.

The interpreter is great for debugging hardware.  The compiler is great for writing test programs.   if your MCU does not support a particular type of I/O, this makes a great I/O co-processor.   It is running on the  $38 Pico2 Ice, and can be ported to your favourite FPGA board. It is also great for people who want a simple development environment, free of excess layers of abstraction.  It has:

• 16 bit words.
• 256 deep data and return stacks.
• 64K words of on chip memory on the ICE40 UP5K FPGA.
• Single Clock Cycle per Forth Instruction (Arm takes 2-3 clock cycles per ARM assembly instruction).
• Single clock cycle interrupts.
• Compact Programs (2 Bytes/Forth Instruction. (Gforth takes 19-23 32 bit ARM ASM words per Forth instruction). 
• Single step debugging from the second core. 
• Based on the Industry proven, open source Mecrisp Ice J1 soft core.
• Well documented. 
• Hardware Error Checking.
• 214 line cross-compiler (GCC is 13 million lines).
• Access to vast C libraries on the Microcontroller.
• USB-C 2.0 power and control.
• 3 FPGA PMODs.
• Mac OS and Linux simulators available. 

Pico Ice Version 

• 133 Mhz RP22040 MCU.
• 1 Additional RP2350 PMOD (USB Host mode possible via PIO).
• 2 Quad DDR SPI RP2350 <-> FPGA interfaces at 75Mhz (Full Duplex).
• FPGA Flash.
• FPGA 8MB low power qSPI SRAM

Pico2 Ice Version 

Limited by RP2350 availability.

• 150 Mhz RP2350 MCU.
•  DVI output.
• 1 Additional RP2350 PMOD (USB Host mode possible via PIO).
• 2 Quad DDR SPI RP2350 <-> FPGA interfaces at 75Mhz (Full Duplex).
• FPGA Flash.

ICE-V Wireless Version 

Reportedly the Pico-Ice bitstream also works on the Ice-V Wireless board.

• 66 Mhz ESP32-C3.
• Wifi.
• Bluetooth.
• Battery and charging circuitry.
• 60 Mhz  Quad SPI ESP32 <-> FPGA Interface (Hałf Duplex).
• FPGA external RAM. 

When debugging hardware, an interpreter is invaluable.  Other interpreters such as Python and LUA have garbage collectors, which do not work well with real time data processing.  Applications built with this technology require 60% less memory than applications built on RISC-V,  Since off-chip memory access requires more than 100 times as much power as on-chip memory access, this can lead to dramatic power savings. 

The initial version supports warm boot.  Additional functionality is being rapidly added.  What do you need? I would very much like to help your project.