A Family of Many Core Forth Processors

Hana ( 花 Flower in Japanese) is a family of 16 bit many core Forth processors built on FPGAs. The Hana cores are based on the popular J1 cores, and its successor the Mecrisp cores. Unlike the J1, and Mecrisp, the Hana cores will even runs on single port memory.

Hana 1 is a single core Mecrisp-Ice Forth processor built on the $28 Pico-Ice using the Lattice UltraPlus ICE40UP5K. 

Hana UXN will implement the UXN opcodes.  They are remarkably similat to Forth words.  The big difference is how literals are handed.  The UXN literal opcode puts the cpu in a different state, so that the next word is interpreted as a literal.  In contrast Forth instrucitons use the first bit to indicate if an instruciton is a literal or not.

The Hana 4 will be a four core Forth Processor 4 large Forth cores will each have 16 K of 16 bit words Two of them will support 8 Coroutines.  Two of them will support 4 coroutines.

Hana 16 will be a sixteen core Forth processor built on the ULX3, or soon ULX4, using the ECP5 FPGAs.

Hana 400 will be a 400 core Forth processor, each with 1/2 Mbit of RAM,  built on the largest Xilinx chips.  Just waiting for someone to send me the board!

  FPGA Chips and Boards

  Hearing Aids

  Input and Output

  J1 and Mecrisp

  Memory Management

  Progress Report


  Review of Existing Forth Cores

  MicroPython on the Pico-Ice

  Ship Schedule

  Pico Ice Echo Server


  Hana UXN

  J1 Stacks

  Documentation of J1 Versions.

  Review of J1 Versions Source Code

  Review of Silesian Politechnical Digital Design Masters Program (MSC)

 Built using the  Forest Map Wiki