A Family of Many Core Forth Processors
Hana ( 花 Flower in Japanese) is a family of 16 bit many core Forth processors built on FPGAs. The Hana cores are based on the popular J1 cores, and its successor the Mecrisp cores. Unlike the J1, and Mecrisp, the Hana cores will even runs on single port memory.
Hana 1 is a single core Mecrisp-Ice Forth processor built on the $28 Pico-Ice using the Lattice UltraPlus ICE40UP5K.
Hana UXN will implement the UXN opcodes. They are remarkably similat to Forth words. The big difference is how literals are handed. The UXN literal opcode puts the cpu in a different state, so that the next word is interpreted as a literal. In contrast Forth instrucitons use the first bit to indicate if an instruciton is a literal or not.
The Hana 4 will be a four core Forth Processor 4 large Forth cores will each have 16 K of 16 bit words Two of them will support 8 Coroutines. Two of them will support 4 coroutines.
Hana 16 will be a sixteen core Forth processor built on the ULX3, or soon ULX4, using the ECP5 FPGAs.
Hana 400 will be a 400 core Forth processor, each with 1/2 Mbit of RAM, built on the largest Xilinx chips. Just waiting for someone to send me the board!
Hearing Aids
Hearing aids are a great application for these processors. #hearing-aids
Input and Output
I expect the I/O organization to evolve rapidly in response to user requirements. So please treat this as a preliminary document. #io
J1 and Mecrisp
J1 is a gorgeous cpu, Mecrisp makes it useful, Hana makes it inexpensive. #j1-and-mecrisp
Memory Management
Memory is the limiting resource on the Ice40 FPGA's. #memory-management
24 bit Memory Management
A future release will support 24 bit words. This document tells you how that will work. #memory-management-24
Progress Report
Here I document the plans and the progress. #progress-report
contact
How to contact me. #contact
Review of Existing Forth Cores
I will be resenting a talk at SVFIG in August and at FPGA World in Stockholm in September. #review-of-existing-forth-cores
Ship Schedule
My best guess on when this will ship. #ship-schedule
Pico Ice Echo Server
This page describes the pico-ice echo server, which is used to debug passing text from the USB through the RP2040 and to the FPGA. #pico-ice-echo-server
BAD URL
Bad URLs redirect here. #categories
Hana UXN
Hana UXN will support the UXN opcodes. #hana-uxn
J1 Stacks
An overview of the different versions of stacks available for the J1. #j1-stacks
Documentation of J1 Versions.
There are many many different versions of the J1 processor. Here I will introduce them. #documentation-of-j1-versions
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