A Family of Many Core Forth Processors --> J1 and Mecrisp

J1 and Mecrisp

J1 is a gorgeous cpu, Mecrisp makes it useful, Hana makes it inexpensive.


First let me describe the J1.  The J1 is very simple. Less than 200 lines of Verilog.  The J1 is very fast.  80Mhz.  The J1 is very small.  160 LUTs with the barrel shifter, 80 with a single bit shifter.  It is great to read the source code to understand what a stack machine is.  It is a very parallel stack machine.  Depending on the Forth word executed, multiple different things happen at the same time.  And finally it is a very popular CPU, lots of different incarnations.    But ti does have its limitations.  The J1 does not have:


 Mecrisp makes the J1 useful.  Mecrisp-Ice is the upgraded CPU.  Mecrisp Stellaris provides the software to run on it.  The Mecrisp hardware adds the following to the J1:

  1. Interrupts with a fixed latency of two cycles.
  2. A tick counter,
  3. MSP430 style IO ports,

The Mecrisp Stellaris software provides:

  1. Constant folding,
  2. Inlining
  3. Tail-call optimisations,
  4. A large Forth library including
  5. FFT.
  6.  Load & Save from and to SPI flash with init mechanism,
  7. More readable disassembler,
  8. Dictionary structure insight,

Mecrisp includes directories with build commands for the following platforms:

There is also an unofficial and out of date port of the Mecrisp processor to the UPduino, which is the board I am starting with, and will soon be recommending.

There is a github repository for Mecrisp-Ice, but it is out of date.  What you want to do is to grab the gzip file from source forge.  If you want to make any changes, you can discuss them with the author on sourceforge, and email him the changes.

If you are just getting started with Mecrisp, the first thing to do is to get the tools working.  Create a blinking light demo.  Once the tools are working for you, get the verilator working, and then proceed to getting Mecrisp working.


The problem with the J1 and Mecrisp-Ice CPUs is that they require dual port memory.  Dual port memory can be read to or written to by two different processes every clock cycle.  The J1 fetches an instruction every cycle, and just in case it needs it, it read from memory every cycle.   The problem is that the less expensive ICE-40 CPUs only have 120Kbits of dual port memory.  But they have 1Mbit of single port memory which the J1 cannot use.  The goal of the Hana CPU is to make the J1 work on single port memory.    That will enable people to use it on the less expensive and beautiful Pico-Ice and Upduino boards.

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