Ths simplest GateMate display option is to use the VGA output port on the €50-€54 Olimex GateMate board.   Here are 3 Olimex GateMate VGA demos.  There are many more VGA demos which were used for testing  Nextpnr placement for GateMate.  Once you have VGA working, you can then connect it to a VGA -> USB dongle.  Read more here.  But these VGA solutions limit you to 640x480 @60FPS.  

For higher resolution, one can use DVI or HDMI.     HDMI is a proprietary superset of DVI and includes audio inserted into the empty frame around the image (front and back porch).  This Hackaday article does a great job covering the electronics part of the topic.   "Beginning FPGA Graphics" goes into more detail. DVI and HDMI use Transition-minimized differential signalling (TMDS).    TMDS uses current-mode logic with open-collector drivers. GateMate differential signalling can drive TMDS.

DVI runs on top of the TMDS physical layer. DVI is a free standard for transmitting video. DVI allocates one differential pair to each color, and one pair to the clock. DVI has horizontal and vertical sync signals, and an empty frame around the image (the porch). DVI encodes 8 bits of color in 10 bits. DVI can run at speeds from 24.5Mhz (640*480 @60Hz) (easy to debug) up to 161+ Mhz (1600 × 1200 @ 60 Hz). Dual Channel DVI supports twice as much data, and can run at higher frequencies. Here are two GateMate DVI repositories, and three more.   

To use DVI with GateMate one needs to connect to a DVI/HDMI port.  If your board does not include a port, you can use the shipping SiPeed PMOD DVI Module

Or, if they are available, you can buy the  more expensive European  MacDyne DDMI PMOD Module (€17.95).  Just don't plug them into a PMOD port.  PMODs expect 3.3v output.  The GateMate generates 2.5V output.  To convert between voltages level shifters are used, but some level shifters support a maximum frequency of 100Mhz.  Check the particular PMOD level shifter for what frequency it will support. 

Better yet use the Open Source Olimex GateMate DVI-IO board shown below, they plug directly into one of the 20 pin ports on the board, but you have to manufacture them yourself. 

In a private conversation, Cologne Chips tech support said that "If you manage to implement a GateMate serializer at 371.25 MHz, you can also do 720p60 (1280×720@60FPS) or 1080p30 (1920 × 1080@30FPS) on the GateMate, without any external TMDS chip." 

The GateMate can do 8x8 bit multiplies at 150Mhz, so I think that it is possible to do a small circuit on the outside of the CDC FIFOs with hard placement of the output shift registers, which may be able to achieve  that frequency.  If it is an 16 bit shift register, then one has 16 clock cycle for the data to reach from the FIFO CDC to the periphery before being shifted into adjacent shift register cells.  

The best solution may be to use a dedicated chip for 24 bit parallel to TDMS conversion.  TFP410  by Texas Instruments provides a bridge between a parallel single ended video interface and DVI/HDMI. It supports up to 24bit 1600x1200 pixels at 165Mhz. Input can be 12 bits wide DDR, or 24 bits wide SDR.  SIL164 by Lattice Semi also bridges RGB to DVI. Either TFP410 or SIL164 can be used in the 1BitSquared DVI output PMOD (€22) pictured below or the Adafruit DVI/HDI (input) Decoder ($30).   

One can plug the DVI PMOD directly into the Colgne Chips board, the PMOD are correctly spaced.  You can see the picture below.   Cologne Chips Tech support said: "I achieved up to 148.5 MHz. That is 1080p and it works.  You might want to set the core voltage to 1.15V."  I have that code on my desk. 


 Or you can plug the DVI PMOD into the Open Source Olimex GateMate dual PMOD IO Board.  But you have to manufacture them yourself. 


In either case just check the maximum supported frequency of the level shifters.  And of course the highest bandwidth solution is to have a GateMate circuit board incude either the TI TFP410 or the Lattice  SIL164 with short wires connected directly to the FPGA. 

DVI INPUT
There are many DVI output solutions for FPGAs, but a shortage of DVI input solutions for FPGAs.  There is a closed source Xilinx DVI input solution IP, and a low bandwidth DVI input solution for the ECP5 ULX3M boards.

 Built using the  Forest Map Wiki