A Family of Many Core Forth Processors --> Review of J1 Versions Source Code

Review of J1 Versions Source Code

I have been reading the source code of many different versions of the J1.

I have gone through every line of Verilog code of the J1, J1a most of mecrisp and much of the SpinalHDL of the J1Sc.  The J1 is gorgeous, simple and sweet, but very limited. Only 16 instructions, no timer, no interrupts.   The Swapforth repository adds in the Forth required to do anything, but swapforth/verilog/j1.v is a nightmare to understand.   It supports pseudo dual port RAM, but the code changes were literally impossible to understand, and the documentation does not help much.   Figuring it out was like assembling a jig saw puzzle.

swapforth/icestorm/j1a.v makes things worse.  Adds in a bunch of junk I do not need.

Mecrisp is a big improvement.  Adds in a timer, interrupt,  operations on two 16 bit words, and quite a few nice comments.  Once one understands the swapforth J1, mecrisp is a pleasure to read.   Of course it is now too big, 2500 + luts,


I did shrink the Mecrisp Forth core from 

2604/ 5280  49% Luts


1944/ 5280  36%. of Luts

Getting rid of the barrel shifter saves another 100 luts. No point.

But moving the stacks to the freed up PSRAM should shrink it quite far.
 ICESTORM_LC:   976/ 5280    18%

Meaning that 4 cores should be easily doable.

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