A Family of Many Core Forth Processors --> J1 Stacks

J1 Stacks

An overview of the different versions of stacks available for the J1.

In the J1 and Mecrisp-Ice worlds, there are several different versions of stacks: stack, stack2, stack3  bramstack, and they can be 16, 32, or 64 bits wide. 

So first we have the original J1 stack. Quite simple really.  We have an array, basically some memory 2**4 - 16 deep.   There is a write address, a read address, write data, read data, and write enable.   Could not be simpler. 
Sadly the others are harder to understand.

Here is the Bowman stack for a 4 unit barrel processor.  A barrel processor has multiple hardware threads all sharing the same ALU.  The processor shifts every clock cycle.    Basically there are 4 different stack, one for each barrel, and the output has a delay so that the stacks output is always correct for each barrel. 

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