A Family of Many Core Forth Processors --> Input and Output

Input and Output

I expect the I/O organization to evolve rapidly in response to user requirements. So please treat this as a preliminary document.

The Upduino has 56 GPIO pins, two SPI cores, two I2C cores, 4 optional pMods, and some pio blocks.  Initially each Forth core will drive 14 pins including the 4 that control one of the pMods.  There will be an option for each pMod to be driven by a UART.   The SPI and I2C cores will be divided among the 4 Forth cores.   Long term I expect to move to using small Mecrisp 16 bit prociessors, using the blocs to drive pins.

As various pmods are tested and proved to be working, they will be documented here.  Until then, please proceed cautiously with I/O.  And please let me know your requirements.


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